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Cache Verification
Unit Verification and Core Technologies
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CacheLoader
The CacheLoader is a technology that is used in hardware verification for initializing caches. Systems that have microprocessors typically include several levels of cache storage. During verification of these systems, the caches should be initialized both in a coherent state and in interesting combinations. The main role of the CacheLoader is to receive the initialization requests together with other preferences, and to generate a random-biased initialization of the storage in the system.
The CacheLoader is built as a model-based Building Block and it is planned to be used at several different levels of verification, including unit, core, nest, chip, and system levels. This application is planned to be integrated into the Fusion environment, but its independent architecture (the Building Block concept) allows integration into other environments as well.
The CacheLoader is not only responsible for adequate cache initialization in the pre-simulation phase, it also allows dynamic cache re-initialization during simulation to further increase the singularity and incisiveness of the running test case.
The main advantage of the new CacheLoader is its model (architectural description and testing knowledge - the Model-based concept) that defines the structure of the caches in the system, the coherency rules, and the biasing rules. This model is based on a dedicated language that is built for a storage sub-system with a GUI that enables population of this model. It means that the core of the CacheLoader is generic and does not change between designs. Part of this core reads the details from the model and acts upon them. This method allows convenient encapsulation of the domain knowledge and also makes it available and understandable. The power of the technology increases with the number of the generic biases. Both the biases and coherency rules are written using the same supported language.
The initialization request for the CacheLoader includes the address set that is used, directives describing the biasing rules in effect (on top of the default ones), and more. The supported biases have a scope: users have the option of associating biases not just with the whole system, but with any of its parts. In addition, users can populate addresses into selected caches, or in extreme cases, they can determine specific values for specific fields of the caches. The association of a user request for each initialization enables to generate different initializations for the various parts of the system, and different re-initializations during simulation.
CML
Coherence Monitor Lite (CML) is an implementation of a verification framework targeted specifically at the system level of simulation. It is designed to detect the type of bugs that typically arise from the interaction of components in a complex SMP or Clustered system. CML consists of an API for development and execution of checkers, a graphical simulation debugger, a coverage data generation engine, and several hundred portable system-level checkers.
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