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IBM's formal verification technologies have been licensed by several EDA tool providers in order to power advanced verification products.
One technlogy that has triggered wide interest is IBM's PSL synthesis engine. This technology, embodied in the IBM FoCs tool, converts PSL assertions into optimized assertion-checking code - e.g. in synthesizable VHDL/Verilog or C/C++. Another key technology is IBM's high-performance formal analysis engines which enable the exploration of large design spaces against design requirements. Those engines are presently embodied in the IBM RuleBase product family.
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